DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
A data structure for gridless routing
DAC '80 Proceedings of the 17th Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Placement algorithms for arbitrarily shaped blocks
DAC '79 Proceedings of the 16th Design Automation Conference
An automated design of minimum-area IC power/ground nets
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Optimum design of reliable IC power networks having general graph topologies
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Multi-pads, single layer power net routing in VLSI circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Analyzing CMOS power supply networks using Ariel
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A current driven routing and verification methodology for analog applications
Proceedings of the 37th Annual Design Automation Conference
Single step current driven routing of multiterminal signal nets for analog applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Laying the power and ground wires on a VLSI chip
DAC '83 Proceedings of the 20th Design Automation Conference
The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
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For a given placement of macrocells with given power consumption a full automatic layout of power supply and ground nets has been developped. The varying width in different segments of these nets is calculated from local current values resulting in rectangles presenting the net segments. These rectangles are embedded in the routing plane with regard to given design rules.