Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
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Two topologies are proposed at the physical level to achieve reliable power gating in through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs). The proposed lumped and distributed power gating topologies address the unique differences among distinct TSV fabrication methods such as via-first, via-middle, and via-last, while achieving, on average, 85% reduction in the leakage power. Related tradeoffs among power supply noise, power gating noise, physical area, and turn-on time are also investigated.