Modeling magnetic coupling for on-chip interconnect
Proceedings of the 38th annual Design Automation Conference
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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One or 2-step Gauss-Jacobi method is efficiently incorporated to the large scale interconnect analysis. In order to make the Gauss-Jacobi method within 1 or 2 iterations during each time step, the interconnect network is formulated by the RLCG-MNA formulation. In the numerical example, it is illustrated that the one-step Gauss-Jacobi method is 1,035 times faster than Berkeley SPICE and several tens times faster than INDUCTWISE which is known as the recent fast simulation method. Further, we show that the 2- step Gauss-Jacobi method is rational from efficiency and accuracy points of views.