Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Future SOC Design Challenges and Solutions
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Improved model-order reduction by using spacial information in moments
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Equivalent Waveform Propagation for Static Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical analysis methods to reduce the circuit complexity and speedup the simulation. A simple controlled sources model is used for modeling clock buffers to deal with nonlinearity in the buffered clock trees. Our experiment results show that the proposed algorithm is about two orders of magnitude faster than HSPICE without loss on accuracy and stability. The relatively errors on delay times are within a few percent of the exact ones.