Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Synchronous and Asynchronous Parallel Simulated Annealing with Multiple Markov Chains
IEEE Transactions on Parallel and Distributed Systems
Parallel simulated annealing algorithms
Journal of Parallel and Distributed Computing
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Heterogeneous computing and parallel genetic algorithms
Journal of Parallel and Distributed Computing - Problems in parallel and distributed computing: Solutions based on evolutionary paradigms
Congestion Estimation with Buffer Planning in Floorplan Design
Proceedings of the conference on Design, automation and test in Europe
An orthogonal simulated annealing algorithm for large floorplanning problems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Enhanced BSA for Floorplanning
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Design and Analysis of Experiments
Design and Analysis of Experiments
A Parallel Genetic Algorithm for Floorplan Area Optimization
ISDA '07 Proceedings of the Seventh International Conference on Intelligent Systems Design and Applications
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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One of the critical issues in floorplanning is to minimize area and/or wire length of a given design with millions of transistors while considering other factors which may influence the success of design flow or even manufacturing. To deal with the floorplan design with enormous amount of interconnections and design blocks, we adopt a parallel computing environment to increase the throughput of solution space searching. Also, we include the fractional factorial analysis to further reduce the time needed to search the acceptable solution. The experimental results indicate that our approach can obtain better space utility rate and it takes less time than the traditional method and parallel method do.