A Parallel Simulated Annealing Approach for Floorplanning in VLSI
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Solving job shop scheduling problem using a hybrid parallel micro genetic algorithm
Applied Soft Computing
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Floorplanning is an important problem in Very Large- Scale Integrated-circuit (VLSI) design automation as it de- termines the performance, size, yield and reliability of VLSI chips. From the computational point of view, floorplan area minimization is an NP-hard problem. This paper presents a parallel genetic algorithm (GA) for floorplan area opti- mization. The parallel GA is based an island model with an asynchronous migration mechanism, and is implemented using Web services and multithreading technologies. The parallel GA is compared with a sequential GA that the par- allel GA is based on. Experimental results show that the parallel GA can produce better results than the sequential GA when they use the same amount of computing resources. In addition, since the number of islands and migration in- terval are two important parameters that directly affect the performance of island-based parallel GAs, the impact of the two parameters on the performance of the parallel GA are empirically studied in this paper.