Maximum voltage variation in the power distribution network of VLSI circuits with RLC models
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
Analog Integrated Circuits and Signal Processing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Weakness identification for effective repair of power distribution network
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
| Hi-index | 0.00 |
The design, implementation, and verification of the power distribution network for the 5.2 million transistor UltraSPARC-I microprocessor is described. A novel simulation method allows rapid identification of exact layout locations with potential electromigration or excessive voltage drop problems. Hierarchical verification capabilities of this approach are utilized to design an efficient and robust distribution of V/sub dd/ and V/sub ss/ across a large die, in the face of stringent IR drop and floorplanning constraints. A comprehensive methodology for power distribution and management, along with seamless integration of the power distribution into existing CAD tools throughout the design cycle results in correct-by-construction power networks for cell libraries and functional blocks, area efficient power interconnections and reduced time-to-market due to correction of all reliability failures in the power networks prior to mask generation.