Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power supply design parameters prediction for high performance IC design flows
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Proceedings of the 37th Annual Design Automation Conference
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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As device densities and clock frequencies continue to increase in ultra deep-submicron (UDSM) circuits, several aftereffects are becoming predominant and causing performances and reliability problems. Among the more relevant effects in high performance circuits is Power Supply Noise, considered both in the two aspects: Simultaneous Switching Noise and Voltage Drop. These phenomena have as consequences errors or delays on gates connected to noisy references, crosstalk against neighbour quiet lines, substrate noise injection, electromigration, and electromagnetic interference toward neighbour circuits: power grid verification is then becoming a basic step in deep-submicron design.It is no more feasible, as in the past, to face at the end of the design phase power supply noise analysis and solution, because it is too expensive from the time-to-market point of view. For this reason accurate but fast methodologies are explored for power supply noise analysis, and the trend is to insert them in early design stages.In this paper we introduce an algorithm, based on an ad-hoc cell library characterization and on an accurate circuit switching activity evaluation, to analyze Power Supply Noise using a hierarchical Power Grid model and to define power busses design parameters with extremely high accuracy and good performances. The focus of the paper is on the algorithm adopted to evaluate power supply noise using hierarchical power grid description and current activity informations. It has been thought in the same time as a pure analysis procedure, or as a power grid design flow, or as a starting point for a future noise driven placement algorithm.