Maximum current estimation in CMOS circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Towards a high-level power estimation capability
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
The design and implementation of PowerMill
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Fast power loss calculation for digital static CMOS circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Function-level power estimation methodology for microprocessors
Proceedings of the 37th Annual Design Automation Conference
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework
IEEE Transactions on Computers
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
Analog Integrated Circuits and Signal Processing
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Power management is an increasing concern for processor design. In this paper, we presented an overview of traditional power simulation tools and discussed two emerging power management design technologies: power distribution integrity analysis and standby current measurement and optimization. We present methods for accurate peak current simulation, which is needed for power grid integrity analysis, and discuss the generation and compression of the simulation vectors. Also, static approaches for calculating an upper-bound on the maximum peak current are presented. Standby leakage current is state dependent and we present methods for calculating both the average and maximum leakage current. Finally, optimization methods for minimizing the leakage current by either assigning a standby state to the circuit or by using a dual-Vt process are discussed.