Resistance extraction and resistance calculation in GOALIE?
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Time efficient VLSI artwork analysis algorithms in GOALIE2
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
IBM Journal of Research and Development
On the efficacy of simplified 2D on-chip inductance models
Proceedings of the 39th annual Design Automation Conference
Practical considerations in RLCK crosstalk analysis for digital integrated circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Implicit treatment of substrate and power-ground losses in return-limited inductance extraction
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
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In this paper, we report the development of the first commercial full-chip, three-dimensional, shapes-based, RLCK extraction tool, developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate noise analysis. The tool, Assura RLCX, exploits high-capacity scan-band techniques and disk caching for inductance extraction as an extension to Cadence's existing Assura RCX extractor.