Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Digital systems engineering
Full-chip, three-dimensional, shapes-based RLC extraction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Early Capture for Boundary Scan Timing Measurements
Proceedings of the IEEE International Test Conference on Test and Design Validity
A high speed and area efficient on-chip analog waveform extractor
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On-Chip Oscilloscopes for Noninvasive Time-Domain Measurement of Waveforms
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On-chip measurement of waveforms in mixed-signal circuits using a segmented subsampling technique
Analog Integrated Circuits and Signal Processing
An on-chip multichannel waveform monitor for diagnosis of systems-on-chip integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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High-speed digital design is becoming increasingly analog. In particular, interconnect response at high frequencies can be nonmonotonic with "porch steps" and ringing. Crosstalk (both capacitive and inductive) can result in glitches on wires that can produce functional failures in receiving circuits. Most of these important effects are not addressed with traditional automatic test pattern generation (ATPG) and built-in self-test (BIST) techniques, which are limited to the binary abstraction. In this work, we explore the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms on selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve 10-ps timing accuracy. High-speed samplers are combined with delay-locked loops (DLLs) and a simple 8-bit analog-to-digital converter (ADC) to convert the waveforms into digital data that can be incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to incorporate these oscilloscopes with a high-frequency interconnect structure in a TSMC 0.25-µm process. The layout was extracted using Cadence's Assura RCX-PL extraction engine, enabling a comparison between simulated and measured results.