At-speed boundary-scan interconnect testing in a board with multiple system clocks
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A new IEEE 1149.1 boundary scan design for the detection of delay defects
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications
Digital Window Comparator DfT Scheme for Mixed-Signal ICs
Journal of Electronic Testing: Theory and Applications
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function
Journal of Electronic Testing: Theory and Applications
A high speed and area efficient on-chip analog waveform extractor
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design of Digital Window Comparators and their Implementation within Mixed-Signal DfT Schemes
Analog Integrated Circuits and Signal Processing
Static and Dynamic On-Chip Test Response Evaluation Using a Two-Mode Comparator
ETW '00 Proceedings of the IEEE European Test Workshop
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Contactless Digital Testing of IC Pin Leakage Currents
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
P1149.4 " Problem or Solution for Mixed-Signal IC Design?
ITC '97 Proceedings of the 1997 IEEE International Test Conference
IEEE P1149.4 - ALMOST A STANDARD
ITC '97 Proceedings of the 1997 IEEE International Test Conference
The Integration of Boundary-Scan Test Methods to A Mixed-Signal Environment
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Interconnect Delay Fault Testing with IEEE 1149.1
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analog Integrated Circuits and Signal Processing
On-chip measurement of waveforms in mixed-signal circuits using a segmented subsampling technique
Analog Integrated Circuits and Signal Processing
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
System-level specification testing of wireless transceivers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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