Early Capture for Boundary Scan Timing Measurements
Proceedings of the IEEE International Test Conference on Test and Design Validity
Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams
Proceedings of the IEEE International Test Conference
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A sigma-delta modulation based BIST scheme for mixed-signal circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Testing and Characterization of the One-Bit First-Order Delta-Sigma
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
On-chip measurement of waveforms in mixed-signal circuits using a segmented subsampling technique
Analog Integrated Circuits and Signal Processing
System-level specification testing of wireless transceivers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A multiple pass A/D conversion techniqueis proposed for mixed-signal test applications.Only a single on-chip comparator and sample-and-holdcircuit is required to digitize repetitive analog wave-forms.Simulations show 10 bits of amplitude resolutionat 300 MHz for a bipolar comparator design (0.8 mmBiCMOS process), and 10 bits of amplitude resolution at667 MHz for a CMOS comparator design (0.5 mmCMOS process). A prototype IC designed for a 0.5 mmCMOS process has been sent for fabrication. Experimentalresults from a prototype board (implementedwith discrete components) are given.