Implicit treatment of substrate and power-ground losses in return-limited inductance extraction

Authors:
Dipak Sitaram;Yu Zheng;K. L. Shepard
Affiliations:
Cadence Design Systems, New Providence, NJ;Columbia University New York, NY;Columbia University New York, NY
Venue:
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Year:
2002

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Abstract

Full-wave analysis, based on rigorous solution of the differential or integral form of Maxwell's equations, is too slow for all but the smallest designs. Traditional on-chip extraction engines are, therefore, being pushed to extract inductance and provide accurate high-frequency interconnect modelling while maintaining computational efficiency and capacity. This paper describes further accuracy-improving enhancements to the commecial full-chip RLCK extraction engine, Assura RLCX[1], based on the return-limited inductance formulation. Specifically, we incorporate substrate losses due to eddy currents and power-ground losses while, based on design-driven assumptions, avoiding explicit extraction of the power-ground and substrate. Results are validated on small testcases where comparison with full-wave solution is practical.