Plane-sweep algorithms for intersecting geometric figures
Communications of the ACM
DAC '83 Proceedings of the 20th Design Automation Conference
Space efficient algorithms for VLSI artwork analysis
DAC '83 Proceedings of the 20th Design Automation Conference
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
Resistance extraction and resistance calculation in GOALIE?
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Circuit extraction on a message-based multiprocessor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Full-chip, three-dimensional, shapes-based RLC extraction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Industrial strength polygon clipping: A novel algorithm with applications in VLSI CAD
Computer-Aided Design
| Hi-index | 0.00 |
New algorithms used in the GOALIE2 circuit extraction system, based on representing VLSI layout geometries as trapezoids, are presented in this paper. These include polygon-to-trapezoid decomposition, scanline management, and output sorting. In particular, the scanline algorithm virtually eliminates all redundant computation present in similar systems. These algorithms enable us to perform VLSI layout analysis in nearly linear time.