The number of buffers required for sequential processing of a disk file
Communications of the ACM
Mask verification on the connection machine
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Time efficient VLSI artwork analysis algorithms in GOALIE2
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Hierarchical analysis of IC artwork with user defined abstraction rules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Post-Layout Verification of the WE DSP32 Digital Signal Processor
IEEE Design & Test
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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This paper discusses the use of a general purpose, message based multiprocessor to speed up the task of VLSI circuit extraction. The parallel algorithm incorporates the use of secondary storage to allow complete VLSI circuits to be extracted with small scale multiprocessors. The paper presents experimental results for the detection and labelling of transistor regions.