Design rule verification based on one dimensional scans
DAC '78 Proceedings of the 15th Design Automation Conference
Fast algorithms for LSI artwork analysis
DAC '77 Proceedings of the 14th Design Automation Conference
A layout checking system for large scale integrated circuits
DAC '77 Proceedings of the 14th Design Automation Conference
A symbolic design system for integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
Understanding hierarchical design
Understanding hierarchical design
Circuit extraction on a message-based multiprocessor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
RISCE—a reduced instruction set circuit extractor for hierarchical VLSI layout verification
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
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Hierarchical DRC and component extract offer many advantages but no one form of hierarchical analysis fits all situations. This paper introduces hierarchical analysis in which the user specifies how abstract representations of cells are formed, how they are checked, and what to do if a violation is detected. This allows one analysis program (with different rules) to use the designer's hierarchy for a wide variety of different analyses. In particular, analyses that had been difficult in previous schemes (cross coupling capacitances, terminals in the center of cells, multilayer interconnects) can now be handled hierarchically. Topics: 2,5,7