Computational geometry: an introduction
Computational geometry: an introduction
Cost of silicon viewed from VLSI design perspective
DAC '94 Proceedings of the 31st annual Design Automation Conference
Test quality and yield analysis using the DEFAM defect to fault mapper
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Hierarchical analysis of IC artwork with user defined abstraction rules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
DAC '84 Proceedings of the 21st Design Automation Conference
Magic's incremental design-rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
IBM Journal of Research and Development
Modeling of integrated circuit defect sensitivities
IBM Journal of Research and Development
CAD at the design-manufacturing interface
DAC '97 Proceedings of the 34th annual Design Automation Conference
A pattern matching algorithm for verification and analysis of very large IC layouts
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Cost based tradeoff analysis of standard cell designs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Pre-layout prediction of interconnect manufacturability
Proceedings of the 2001 international workshop on System-level interconnect prediction
Defect-oriented test quality assessment using fault sampling and simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Prelayout interconnect yield prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
FedEx - A Fast Bridging Fault Extractor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Algorithm to extract two-node bridges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yield-aware placement optimization
Proceedings of the conference on Design, automation and test in Europe
| Hi-index | 0.00 |
This paper describes an algorithm for efficiently extracting critical area in large VLSI circuits. The algorithm, implemented to handle shorts between electrical nets, takes advantage of the available hierarchy in the layout description in order to speed-up computation and minimize memory usage. The developed software-CREST-was tested for a spectrum of actual IC designs and was found very efficient as compared to existing techniques.