The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Magic's incremental design-rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Copy detection for intellectual property protection of VLSI designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Modeling magnetic coupling for on-chip interconnect
Proceedings of the 38th annual Design Automation Conference
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We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeatable geometrical features and attributes are stored in a pattern database. Original pattern instance, or its geometrical attributes, may be quickly regenerated based both on the information stored within the pattern and position of the pattern instance. We also show preliminary results of analysis of the state-of-the-art ICs which suggest that the diversity of patterns does not significantly increase with the increase of chip size.