Data structures and network algorithms
Data structures and network algorithms
A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Inductive Contamination Analysis (ICA) with SRAM Application
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Integrated Approach for Circuit and Fault Extraction of VLSI Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Test Challenges in Nanometer Technologies
Journal of Electronic Testing: Theory and Applications
FedEx - A Fast Bridging Fault Extractor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Study of Bridging Defect Probabilities on a Pentium (tm) 4 CPU
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
Journal of Electronic Testing: Theory and Applications
Algorithm to extract two-node bridges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On the Characterization of Hard-to-Detect Bridging Faults
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Dynamic Test Compaction for Bridging Faults
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Bilateral Testing of Nano-scale Fault-Tolerant Circuits
Journal of Electronic Testing: Theory and Applications
Resistive bridging fault simulation of industrial circuits
Proceedings of the conference on Design, automation and test in Europe
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Enumeration and prioritization of highly probablebridges based on the circuit layout and manufacturing defectdata is a key step in defect based testing. Existing solutionseither do not scale to large designs or compromiseon the accuracy of the computation when applied to verylarge circuits. This paper presents a scalable and efficientmethodology to accurately extract two node bridges fromvery large circuits. To our knowledge, this is the first solutionto be presented that can process such large industrialdesigns accurately. It also naturally addresses two importantissues viz. through the cell routing and name propagation.Experimental results illustrating key features of the algorithm,including scalability and efficient memory usage,are presented.