A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Improvement of SRAM-based failure analysis using calibrated Iddq testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical area computation via Voronoi diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Test pattern generation and diagnosis algorithms thattarget realistic bridging faults must be provide with arealistic fault list. In this work we escribe FedEx, abridging fault extractor that extracts a circuit from themask layout, identifies the two-node bridges that canoccur, their locations, layers, an relative probability ofoccurrence. Our experimental results show that FedEx ismemory efficient and fast.