Critical area computation for missing material defects in VLSI circuits
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Resistance Characterization for Weak Open Defects
IEEE Design & Test
The Min-Max Voronoi Diagram of Polygons and Applications in VLSI Manufacturing
ISAAC '02 Proceedings of the 13th International Symposium on Algorithms and Computation
FedEx - A Fast Bridging Fault Extractor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On tests to detect via opens in digital CMOS circuits
Proceedings of the 45th annual Design Automation Conference
Hi-index | 0.03 |
This paper describes an algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of industrial size ICs with non-Manhattan geometry. Illustrative examples of the proposed algorithm, implemented by using design rule checker operations, are presented. It is shown that the extraction of the critical area for realistic size VLSI circuits designs can be done in an acceptable time