Critical area computation for missing material defects in VLSI circuits
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
The Min-Max Voronoi Diagram of Polygons and Applications in VLSI Manufacturing
ISAAC '02 Proceedings of the 13th International Symposium on Algorithms and Computation
FedEx - A Fast Bridging Fault Extractor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Robustness of k-gon Voronoi diagram construction
Information Processing Letters
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computing the Map of Geometric Minimal Cuts
ISAAC '09 Proceedings of the 20th International Symposium on Algorithms and Computation
Robustness of k-gon Voronoi diagram construction
Information Processing Letters
Higher order Voronoi diagrams of segments for VLSI critical area extraction
ISAAC'07 Proceedings of the 18th international conference on Algorithms and computation
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In this paper, we present a new approach for computing the critical area for shorts in a circuit layout. The critical area calculation is the main computational problem in very large scale integration yield prediction. The method is based on the concept of Voronoi diagrams and computes the critical area for shorts (for all possible defect radii, assuming square defects) accurately in O(n log n) time, where n is the size of the input. The method is presented for rectilinear layouts and layouts containing edges of slope ±1. As a byproduct, we briefly sketch how to speed up the grid method of Wagner and Koren [1995]