An improved algorithm for constructing kth-order voronoi diagrams
IEEE Transactions on Computers
A new duality result concerning Voronoi diagrams
Discrete & Computational Geometry
Algorithm 447: efficient algorithms for graph manipulation
Communications of the ACM
Farthest line segment Voronoi diagrams
Information Processing Letters
On k-Nearest Neighbor Voronoi Diagrams in the Plane
IEEE Transactions on Computers
Critical area computation via Voronoi diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical area computation for missing material defects in VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nontree routing for reliability and yield improvement [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computing the Map of Geometric Minimal Cuts
ISAAC '09 Proceedings of the 20th International Symposium on Algorithms and Computation
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We address the problem of computing critical area for opens in a circuit layout in the presence of multilayer loops and redundant interconnects. The extraction of critical area is a fundamental problem in VLSI yield prediction. We first model the problem as a graph problem and we solve it efficiently by exploiting its geometric nature. We introduce the opens Voronoi diagram of polygonal objects, a generalization of Voronoi diagrams based on concepts of higher order Voronoi diagrams of segments. Higher order Voronoi diagrams of segments had not received much attention in the literature. The approach expands the Voronoi critical area computation paradigm [1,2,3] with the ability to accurately compute critical area for missing material defects even in the presence of loops and redundant interconnects spanning over multiple layers.