A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems
Journal of Electronic Testing: Theory and Applications
Defect-oriented test quality assessment using fault sampling and simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
FedEx - A Fast Bridging Fault Extractor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Layout-based defect-driven diagnosis for intracell bridging defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault analysis and simulation of large scale industrial mixed-signal circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled, both in Manhattan and 45 degrees geometries. Higher level design data, obtained in the top-down design flow, is used for realistic fault characterization. A sliding window algorithm is extended for fault extraction of non-orthogonal geometries. An accurate critical area evaluation algorithm is proposed, to compute the probability of occurrence of the defects. Over 100,000 transistor ICs are analyzed for bridging defects.