A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
CMOS Standard Cells Characterization for Defect Based Testing
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
FedEx - a fast bridging fault extractor
Proceedings of the IEEE International Test Conference 2001
ATS '96 Proceedings of the 5th Asian Test Symposium
Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Parametric Failures in CMOS ICs " A Defect-Based Analysis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Algorithm to extract two-node bridges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Bridge Defect Diagnosis with Physical Information
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Diagnosing realistic bridging faults with single stuck-at information
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Locating bridging faults using dynamically computed stuck-at fault dictionaries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bridge fault diagnosis using stuck-at fault simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a layout-based methodology to predict the exact physical location of a bridging defect inside a standard cell. It involves a number of techniques. First of all, most likely intracell bridging defects are identified through layout analysis and then converted into equivalent logic models. Next, we use a new defect-oriented formulation to generate test pattern for each candidate defect so as to further enhance the diagnostic resolution. Experimental results indicate that this methodology can remove 90% false defect candidates beyond gate-level diagnosis for four real designs and ISCAS'85 benchmark circuits.