Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
IEICE - Transactions on Information and Systems
Layout-based defect-driven diagnosis for intracell bridging defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
An Effective and Accurate Methodology for the Cell Internal Defect Diagnosis
Journal of Electronic Testing: Theory and Applications
A defect-tolerant accelerator for emerging high-performance applications
Proceedings of the 39th Annual International Symposium on Computer Architecture
Hi-index | 0.00 |
The paper addresses the issue of transistor-level bridging fault diagnosis. While most of the previous bridging fault diagnosis work focuses on the gate-level bridging faults, this method provides a solution to intragate bridging faults diagnosis for the first time. Instead of using any transistor level simulation tools, we develop a transformation technique that allows transistor-level bridging faults to be diagnosed by the commonly used gate-level bridging faults diagnosis tools. Real diagnosis results from Philips designs are presented.