Failure Diagnosis of Structured VLSI
IEEE Design & Test
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnosis of Sequence-Dependent Chips
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On Methods to Improve Location Based Logic Diagnosis
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Effective and Accurate Methodology for the Cell Internal Defect Diagnosis
Journal of Electronic Testing: Theory and Applications
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Improving diagnosis resolution becomes very important in nanometer technology. Nowadays, defects are affecting gate and transistor level. In this paper, we present a new method to volume diagnosis intra-gate defects affecting standard cell Integrated Circuits (ICs). Our method can identify the cause of failure of different intra-gate defects such as bridge, open and resistive-open defects. Our method gives accurate results since it is based on the use of physical information extracted from library cells layout. Our method can also locate intra-gate defects in presence of multiple faults. Experimental results show the efficiency of our approach to isolate injected defects on industrial designs.