Diagnosis of realistic bridging faults with single stuck-at information
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fault dictionary compression and equivalence class computation for sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Bridging Fault Diagnosis in the Absence of Physical Information
Proceedings of the IEEE International Test Conference
Novel optical probing technique for flip chip packaged microprocessors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
The Application of Novel Failure Analysis Techniques for Advanced Multi-Layered CMOS Devices
Proceedings of the IEEE International Test Conference
Dynamic diagnosis of sequential circuits based on stuck-at faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Technique for Logic Fault Diagnosis of Interconnect Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Understanding Yield Losses in Logic Circuits
IEEE Design & Test
Error Diagnosis of Sequential Circuits Using Region-Based Model
Journal of Electronic Testing: Theory and Applications
On per-test fault diagnosis using the X-fault model
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient method for improving the quality of per-test fault diagnosis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improve the Quality of Per-Test Fault Diagnosis Using Output Information
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe
Using test data to improve IC quality and yield
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IEICE - Transactions on Information and Systems
Automated failure population creation for validating integrated circuit diagnosis methods
Proceedings of the 46th Annual Design Automation Conference
Timing-aware multiple-delay-fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Selection of a fault model for fault diagnosis based on unique responses
Proceedings of the Conference on Design, Automation and Test in Europe
An Effective and Accurate Methodology for the Cell Internal Defect Diagnosis
Journal of Electronic Testing: Theory and Applications
On undetectable faults and fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of transition fault clusters
Proceedings of the 48th Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Logic fault diagnosis or fault isolation is the process ofanalyzing the failing logic portions of an integratedcircuit to isolate the cause of failure. Fault diagnosisplays an important role in multiple applications atdifferent stages of design and manufacturing. A logicdiagnosis tool with applicability to a spectrum of logicDFT , ATPG and test strategies including full/almost fullscancircuits with combinational APTG, partial-scan andnon-scan circuits with sequential APTG and to functionalpatterns in general is presented. Novel featuresincorporated into the tool include static and dynamicstructural processing for partial-scan circuits, windowedfault simulation, and diagnostic models for open defectsand cover algorithms for multiple fault diagnosis.Experimental results include simulation results onprocessor functional blocks and silicon results on chipsetsand processors from artificially induced defects andproduction fallout.