Probabilistic mixed-model fault diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Adaptive Techniques for Improving Delay Fault Diagnosis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple Fault Diagnosis Using n-Detection Tests
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Dominance Based Analysis for Large Volume Production Fail Diagnosis
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Accelerating Diagnosis via Dominance Relations between Sets of Faults
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Multiple defect diagnosis using no assumptions on failing pattern characteristics
Proceedings of the 45th annual Design Automation Conference
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enhancing Transition Fault Model for Delay Defect Diagnosis
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Timing-aware multiple-delay-fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The goal of fault diagnosis is to identify a set of candidate faults, or fault locations, that explain an observed faulty output response of a chip. In fault diagnosis procedures that are based on specific fault models, a scoring algorithm can be used for defining sets of candidate faults that include the faults with the highest scores. This paper shows that it is possible to capture the underlying concepts that make fault scoring effective through a graph, which is referred to as the dominance graph. With a test set T used for fault diagnosis, the graph represents the dominance relations between the equivalence classes obtained with respect to T. The observed response Robs of a chip-under-diagnosis is associated with an equivalence class Cobs, and Cobs is added to the dominance graph. A candidate fault set is defined based on the dominance relations that are added to the graph due to the addition of Cobs. Certain properties of these dominance relations point to the type of the defect present in the chip, and the most appropriate algorithm for defining a set of candidate faults based on it.