Timing-aware multiple-delay-fault diagnosis

Authors:
Vishal J. Mehta;Malgorzata Marek-Sadowska;Kun-Han Tsai;Janusz Rajski
Affiliations:
Design For Test Methodology Group, NVIDIA Corporation, Santa Clara, CA;Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA;Mentor Graphics Corporation, Wilsonville, OR;Mentor Graphics Corporation, Wilsonville, OR
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

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Abstract

With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay-fault diagnosis problem and propose a novel approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower-than-nominal clock frequencies. We evaluate the utility of n-detection and timing-aware automatic-test-pattern-generated (ATPG) sets. Experimental results show that using timing-aware ATPG sets yields better diagnostic resolution and results in better delay-defect-size estimations compared to n-detection ATPG sets. We experimentally determined our diagnosis algorithm's sensitivity to delay variations.