Using test data to improve IC quality and yield
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Timing-aware multiple-delay-fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosis of transition fault clusters
Proceedings of the 48th Design Automation Conference
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a methodology for diagnosing arbitrary defects in digital integrated circuits (ICs). Rather than using one or a set of fault models in a cause-effect or effect-cause approach, our methodology derives defect behavior from the test set, the circuit and its response, and the physical neighbors that surround a potential defect location. The defect locations themselves are identified using a model-independent stage. The methodology enables accurate identification of defect location and behavior through validation via simulation using passing and additional diagnostic test patterns. A byproduct of our methodology is the distinction that can be made among stuck-fault equivalencies which results in improved diagnostic resolution. Several types of shorts and opens are used to demonstrate the applicability of our approach to the diagnosis of arbitrary defects.