Resistance Characterization for Weak Open Defects
IEEE Design & Test
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
IC failure mechanisms yesterday, today, tomorrow: implications from test to DFM
Proceedings of the 2006 international symposium on Physical design
Product-representative "At speed" test structures for CMOS characterization
IBM Journal of Research and Development - Advanced silicon technology
Active learning framework for post-silicon variation extraction and test cost reduction
Proceedings of the International Conference on Computer-Aided Design
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The complexity of interactions in today's manufacturing processes makes test structures and experiments inadequate as sole drivers of yield-learning and design-for-manufacturing [DfM]. They must be driven by product impact. Product-impact-oriented test-based learning provides insight into the nature of model-hardware mismatches and variability that exist on and impact real products. That insight can be used to drive both parametric and defect-oriented process actions and DfM.