A Systematic Approach for Diagnosing Multiple Delay Faults
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Incremental Diagnosis and Correction of Multiple Faults and Errors
Proceedings of the conference on Design, automation and test in Europe
On Diagnosing Path Delay Faults in an At-Speed Environment
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path delay fault diagnosis in combinational circuits with implicit fault enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An implicit path-delay fault diagnosis methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-aware multiple-delay-fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As timing requirements in today's advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such algorithms capable of diagnosing multiple delay faults. One method uses multiple transition fault models and the other reasons with ternary logic values, thus achieving model independent diagnosis. Experiments are conducted on IS-CAS'85 combinational and full-scan version of ISCAS'89 se-quential circuits corrupted with multiple transition faults. The performance of both algorithms are evaluated and compared. The results show good efficiency and diagnostic resolution.