Diagnosing multiple transition faults in the absence of timing information
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques to prioritize paths for diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The first nonenumerative framework for diagnosing path delay faults (PDFs) using zero suppressed binary decision diagrams is introduced. We show that fault-free PDFs with certain validated nonrobust test may be used together with fault-free robustly tested faults to eliminate faults from the set of suspected faults. All operations are implemented by an implicit diagnosis tool based on the zero-suppressed binary decision diagram. The proposed method is space and time nonenumerative as opposed to existing methods which are space and time enumerative. Experimental results on the ISCAS'85 benchmarks show that the proposed technique is on average three times more efficient than the existing techniques.