Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Introduction to Algorithms
Failure Diagnosis of Structured VLSI
IEEE Design & Test
An Efficient Method to Identify Untestable Path Delay Faults
ATS '01 Proceedings of the 10th Asian Test Symposium
Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Accelerating Diagnosis via Dominance Relations between Sets of Faults
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Prioritization of Paths for Diagnosis
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Function-based compact test pattern generation for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The path-status graph with application to delay fault simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path delay fault diagnosis in combinational circuits with implicit fault enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact path delay fault coverage with fundamental ZBDD operations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An implicit path-delay fault diagnosis methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient identification of (critical) testable path delay faults using decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Existing techniques for path delay fault (PDF) diagnosis prune fault-free candidates using nonfailing patterns but fail to reduce the size of suspect set significantly. This paper presents two alternative techniques that can be applied in a postprocessing manner to further reduce the suspect set by prioritizing paths using only the failing patterns. Experimental results on the ISCAS benchmarks demonstrate that they are time and memory efficient.