Laerte++: an object oriented high-level TPG for systemC designs
Languages for system specification
Diagnosing multiple transition faults in the absence of timing information
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
Journal of Electronic Testing: Theory and Applications
Fast detection of node mergers using logic implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Hi-index | 0.00 |
An incremental simulation-based approach to fault diagnosisand logic debugging is presented. During each iterationof the algorithm, a single suspicious location is identifiedand fault modeled such that the functionality of the newdesign becomes "closer" to its specification. The methodis based on a simple and, at a first glance, counter-intuitivetheoretical result along with a number of heuristics whichhelp avoid the exponential complexity inherent to the problems.Experiments on multiple design errors and multiplestuck-at faults confirm its effectiveness and accuracy, whichscales well with increasing number of errors.