On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With nanometer processes, at-speed testing is required to filter out failing chips with delay defects to ensure high product quality. Locating delay defects is important not only for improving yield but also providing important information to enhance at-speed test methods to meet quality goals. In this paper, a method that leverages successful static defect diagnosis method to diagnose delay defects is presented. To avoid missing any defect suspects, transition fault model is used with special considerations of self masking, glitch detection and passing bit mismatch. The effectiveness of this approach is demonstrated with simulation experiments as well as two case studies on failing chips from Renesas Technology's 130nm process.