A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A Systematic Approach for Diagnosing Multiple Delay Faults
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on Test and Design Validity
A new path-oriented effect-cause methodology to diagnose delay failures
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
Timing-reasoning-based delay fault diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of transition fault clusters
Proceedings of the 48th Design Automation Conference
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents adaptive techniques for improving delay fault diagnosis. These techniques reduce the search space for direct probing which can save a lot of time during failure analysis. Given a set of two-pattern tests that resulted in faulty output responses, a procedure for deriving additional two-pattern tests that will improve the diagnostic resolution of delay faults is described. Two new techniques based on adjacency testing and delay-size bounding are presented. These techniques can be used to greatly reduce the number of suspect lines and thereby provide a more precise diagnosis that is valid for either single or multiple delay faults. Experimental results are shown indicating that the number of suspects can be reduced dramatically for both single and multiple delay faults.