A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay-verification and synthesis of delay-verifiable circuits
Delay-verification and synthesis of delay-verifiable circuits
A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Identification and Test Generation for Primitive Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On diagnosis of pattern-dependent delay faults
Proceedings of the 37th Annual Design Automation Conference
Efficient diagnosis of path delay faults in digital logic circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
IEEE Transactions on Computers
Adaptive Techniques for Improving Delay Fault Diagnosis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Test Application
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fault Diagnosis and Fault Model Aliasing
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selection of a fault model for fault diagnosis based on unique responses
Proceedings of the Conference on Design, Automation and Test in Europe
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved diagnosis using enhanced fault dominance
Integration, the VLSI Journal
Diagnosis of transition fault clusters
Proceedings of the 48th Design Automation Conference
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A new methodology to diagnose delay failures is described.Key characteristics of the methodology are (a) path-orienteddiagnosis, (b) effect-cause reasoning, and (c) utilization of informationobtained from the passing vectors. Two new representationsare developed to make manageable the complexityof a path-oriented methodology. The results of diagnosis are(a) proven to include all possible causes of observed delay errors,and (b) empirically found to have very high resolution.