Failure Diagnosis of Structured VLSI
IEEE Design & Test
Making cause-effect cost effective: low-resolution fault dictionaries
Proceedings of the IEEE International Test Conference 2001
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
An Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Tuples in Diagnosis of Deep-Submicron Circuits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
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Per-test fault diagnosis methodology has been shown to be an effective one for the identification of complex defects. We improve a recent per-test technique by applying additional diagnosis on the outputs of the circuit. The new method brings in more evidence to support the true failures, hence improves the diagnostic quality. We show that this method can very well address several problems in previous work.