A comparative study of design for testability methods using high-level and gate-level descriptions
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Universal fault simulation using fault tuples
Proceedings of the 37th Annual Design Automation Conference
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Making cause-effect cost effective: low-resolution fault dictionaries
Proceedings of the IEEE International Test Conference 2001
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Techniques to Encode and Compress Fault Dictionaries
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Tuples in Diagnosis of Deep-Submicron Circuits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Dictionary Size Reduction through Test Response Superposition
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Gate Level Fault Diagnosis in Scan-Based BIST
Proceedings of the conference on Design, automation and test in Europe
Testing of Digital Systems
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis
Proceedings of the conference on Design, automation and test in Europe - Volume 1
On per-test fault diagnosis using the X-fault model
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
| Hi-index | 0.00 |
Per-test fault diagnosis has become an effective methodology for the identification of complex defects. In this paper, we improve a recent per-test technique by applying additional diagnosis on the outputs of the circuit. The new method does not require additional information than the existing method, but incorporates more evidence to support the true defective sites by using both failing tests and failing outputs information, hence diagnosis quality can be improved. We present the procedure of the new method and give a theoretical analysis. We show that this method can very well address several drawbacks of the previous work. The experimental results on benchmark circuits demonstrate that the new method can significantly improve diagnostic quality compared to other recent results.