Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Tuples in Diagnosis of Deep-Submicron Circuits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Persistent Diagnostic Technique for Unstable Defects
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Systematic Defects in Deep Sub-Micron Technologies
ITC '04 Proceedings of the International Test Conference on International Test Conference
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations
ITC '04 Proceedings of the International Test Conference on International Test Conference
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Diagnosis of Full Open Defects in Interconnecting Lines
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Precise failure localization using automated layout analysis of diagnosis candidates
Proceedings of the 45th annual Design Automation Conference
Controlling DPPM through Volume Diagnosis
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Defect Modeling Using Fault Tuples
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Integrated circuit (IC) diagnosis typically analyzes failed chips by reasoning about their responses to test patterns to deduce what has gone wrong. Current trends use diagnosis as the first step in extracting valuable information from a large population of failing ICs that include, for example, design-feature failure rates and defect-occurrence statistics. However, it is difficult to examine the accuracy of these techniques because of the unavailability of sufficient fail data where such information is known. This paper describes an approach for benchmarking and verifying diagnosis techniques through failure population creation that builds on prior work in this area. Specifically, we describe how a population of realistic IC failures is created through circuit-level simulation of extracted layouts. The most novel feature of the work is that the virtual test responses produced are both a precise function of defect type and the three-dimensional location within the layout. The extended approach is demonstrated using twelve placed-and-routed circuits. An example application of the developed framework is given to illustrate the utility of having a failure population where the location and type of defect are known a priori.