Failure Diagnosis of Structured VLSI
IEEE Design & Test
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Fault Diagnosis for Static CMOS Circuits
ATS '97 Proceedings of the 6th Asian Test Symposium
Diagnosis Of Byzantine Open-Segment Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On per-test fault diagnosis using the X-fault model
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interconnect Open Defect Diagnosis with Physical Information
ATS '06 Proceedings of the 15th Asian Test Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel X-fault simulation with critical path tracing technique
Proceedings of the Conference on Design, Automation and Test in Europe
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Per-test diagnosis based on the X-fault model is an effective approach for a circuit with physical defects of non-deterministic logic behavior. However, the extensive use of vias and buffers in a deep-submicron circuit and the unpredictable order relation among threshold voltages at the fanout branches of a gate have not been fully addressed by conventional per-test X-fault diagnosis. To take these factors into consideration, this paper proposes an improved per-test X-fault diagnosis method, featuring (1) an extended X-fault model to handle vias and buffers and (2) the use of occurrence probabilities of logic behaviors for a physical defect to handle the unpredictable relation among threshold voltages. Experimental results show the effectiveness of the proposed method.