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The purpose of this paper is to present a novelmethodology for the estimation of VLSI products DefectLevel, or reject rates, in the IC design environment. A newDefect-Oriented (DO) fault extraction and stratifiedsampling technique, implemented in an extraction tool,lobs, is used with a novel DO fault simulation tool,veriDOFS, which uses a commercial Verilog simulationtool. The proposed methodology allows the evaluation ofDL values with limited confidence intervals, using reducedfault samples. Results, for a s38417 benchmark circuit(almost 100,000 transistors and over 140,000 extractedbridging defects) lead to test quality validation with 2,000sampled faults.