Object oriented design with applications
Object oriented design with applications
Object-oriented modeling and design
Object-oriented modeling and design
Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
How VSIA Answers the SOC Dilemma
Computer
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
IEEE Design & Test
Design for Testability in Hardware-Software Systems
IEEE Design & Test
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect-oriented test quality assessment using fault sampling and simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On the decline of testing efficiency as fault coverage approaches 100%
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Defect level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, emphasis is given to architecture generation, reconfiguration and quality assessment. Quality metrics and criteria, focused on design and test issues, are used for the purpose. At physical level, a Defect-Oriented Test (DOT) approach and test reuse is the basis of the methodology to estimate test effectiveness, or Defects Coverage. Tools, that implemented the methodology, are presented. Results are shown for a public domain PIC processor, used as a SOC embedded core.