IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays
IEEE Transactions on Computers
FedEx - A Fast Bridging Fault Extractor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Correlation of Logical Failures to a Suspect Process Step
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases off certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache.