Field-programmable gate arrays
Field-programmable gate arrays
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Testing of uncustomized segmented channel field programmable gate arrays
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Introduction to IDDQ testing
Bridging fault detection in FPGA interconnects using IDDQ
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Test Generation for Current Testing (CMOS ICs)
IEEE Design & Test
Testing Defects in Scan Chains
IEEE Design & Test
IDDQ Test and Diagnosis of CMOS Circuits
IEEE Design & Test
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Using ILA Testing for BIST in FPGAs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Improvement of SRAM-based failure analysis using calibrated Iddq testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Low Cost Test Solution for IDDQ
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
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This paper presents an IDDQ-based test strategy for detecting bridging faults in the logic resources of reprogrammable Field Programmable Gate Arrays (FPGAs). The proposed approach utilizes the programmability of the Configurable Logic Blocks (CLBs) to achieve 100 percent coverage of IDDQ-testable bridging faults. We use a hieararchical approach for generating tests and configurations. At the chip level, the CLBs are viewed as a homogeneous two-dimensional array. Two configuration strategies are suggested to simultaneously test each CLB. Within each CLB, we test for external bridging faults between the combinational and sequential logic modules (e.g., flip-flops, multiplexers, lookup tables). Finally, we test for internal bridging faults within each module based on their implementation. Since reconfiguration programming time dominates total test time, even with slow IDDQ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first and, then, to minimize the number of test vectors. The Xilinx XC4000 family of SRAM-based FPGAs is used as an example application of the proposed approach. One hundred percent coverage for IDDQ-testable bridging faults is achieved in five programming phases and 16 IDDQ vectors. Since the lookup tables in the CLB can be configured as RAM, the RAM modes are also tested. This requires a further phase, using 48 test vectors and 38 IDDQ measurements.