Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays
IEEE Transactions on Computers
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
Diagnosis of interconnect faults in cluster-based FPGA architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BIST-Based Delay Path Testing in FPGA Architectures
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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This paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) Field Programmable Gate Arrays (FPGAs). The proposed approach detects bridging faults and is based on quiescent current (IDDQ monitoring. Compared with previous voltage-based methods, IDDQ testing has the advantage of utilizing a small number of programming phases for configuring the FPGA during the test process with negligible observability requirements, even under multiple faults. Algorithms for test generation which exploit the homogeneous nature of the FPGA array, are described. An example using the XC4000 is described in detail. For testing the XC4000 series interconnect, a total of 20 phases and 11 vectors are required: 11 phases for S (switch) block testing, and 9 phases for C (connection) block testing.