Field-programmable gate arrays
Field-programmable gate arrays
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Testing of uncustomized segmented channel field programmable gate arrays
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Introduction to IDDQ testing
Bridging fault detection in FPGA interconnects using IDDQ
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A computer-aided testing framework for field programmable gate arrays: from verification to configuration
Test Generation for Current Testing (CMOS ICs)
IEEE Design & Test
Testing Defects in Scan Chains
IEEE Design & Test
IDDQ Test and Diagnosis of CMOS Circuits
IEEE Design & Test
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Using ILA Testing for BIST in FPGAs
Proceedings of the IEEE International Test Conference on Test and Design Validity
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Low Cost Test Solution for IDDQ
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Back annotation of physical defects into gate-level, realistic faults in digital ICs
ITC'94 Proceedings of the 1994 international conference on Test
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
A Discussion on Test Pattern Generation for FPGA—Implemented Circuits
Journal of Electronic Testing: Theory and Applications
Analyzing the Test Generation Problem for an Application-Oriented Test of FPGAs
ETW '00 Proceedings of the IEEE European Test Workshop
IS-FPGA: A New Symmetric FPGA Architecture with Implicit SCAN
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
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This paper presents an IDDQ-based test strategy for detectingbridging faults in the logic resources of reprogrammableField Programmable Gate Arrays (FPGAs). Theapproach utilizes the programmability of the ConfigurableLogic Blocks (CLBs) to achieve 100% coverage of IDDQ-testablebridging faults. Since reconfiguration programmingtime can dominate total test time, even with slow IDDQ vectors,we use a bottom-up test generation approach to minimizethe number of programming phases first, and then tominimize the number of test vectors. 100% coverage forIDDQ-testable bridging faults is achieved in 5 programmingphases and 16 IDDQ vectors in the Xilinx XC4000 FPGAfamily. The RAM modes are tested in a further phase, using48 test vectors and 38 IDDQ measurements.